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| ? 2002 microchip technology inc. ds21459b-page 1 tc7129 features ? count resolution: 19,999 resolution on 200mv scale: 10 v true differential input and reference low power consumption: 500 aat9v direct lcd driver for 4-1/2 digits, decimal points, low battery indicator, and continuity indicator over range and under range outputs range select input: 10:1 high common mode rejection ratio: 110db external phase compensation not required applications full featured multimeters digital measurement devices device selection table general description the tc7129 is a 4-1/2 digit analog-to-digital converter (adc) that directly drives a multiplexed liquid crystal display (lcd). fabricated in high performance, low power cmos, the tc7129 adc is designed specifi- cally for high resolution, battery powered digital multi- meter applications. the traditional dual slope method of a/d conversion has been enhanced with a succes- sive integration technique to produce readings accu- rate to better than 0.005% of full scale, and resolution down to 10 v per count. the tc7129 includes features important to multimeter applications. it detects and indicates low battery condi- tion. a continuity output drives an annunciator on the display, and can be used with an external driver to sound an audible alarm. over range and under range outputs and a range change input provide the ability to create auto-ranging instruments. for snapshot read- ings, the tc7129 includes a latch-and-hold input to freeze the present reading. this combination of features makes the tc7129 the ideal choice for full featured multimeter and digital measurement applications. typical application package code pin layout package temperature range TC7129CPL normal 40-pin pdip 0 cto+70 c tc7129ckw formed 44-pin pqfp 0 cto+70 c tc7129clw ? 44-pin plcc 0 cto+70 c tc7129 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 9v + + low battery continuity v+ 5pf 120khz 10pf 0.1 f 20 k ? 0.1 f 100k ? 1 f 0.1 f 150k ? 10k ? v+ v in ? + * *note: rc network between pins 26 and 28 is not required. 330k ? 4-1/2 digit analog-to-digital converters with on-chip lcd drivers
tc7129 ds21459b-page 2 ? 2002 microchip technology inc. package type 33 34 35 36 37 38 39 13 10 9 8 7 18 19 20 21 23 24 6543 144 2 22 43 42 41 40 25 26 27 28 32 14 31 15 30 16 29 17 11 12 tc7129clw f 1 , e 1 , dp 1 b 2 , c 2 , batt a 2 , g 2 , d 2 f 2 , e 2 , dp 2 b 3 , c 3 , minus a 3 , g 3 , d 3 f 3 , e 3 , dp 3 b 4 , c 4 , bc 5 a 4 , g 4 , d 4 f 4 , e 4 , dp 4 nc ref lo ref hi in hi in lo buff c ref - c ref + common continuity int out nc a 1 , g 1 , d 1 b 1 , c 1 , cont annunciator osc3 osc1 nc osc2 dp 1 dp 2 range dgnd bp 3 bp 2 bp 1 v disp dp 4 /or nc dp 3 /ur latch/hold v+ v- int in 27 28 29 30 31 32 33 7 4 3 2 1 tc7129ckw 12 13 14 15 17 18 44 43 42 41 39 38 40 16 37 36 35 34 19 20 21 22 26 8 25 9 24 10 23 11 5 6 a 1 , g 1 , d 1 b 1 , c 1 , cont annunciator osc3 osc1 nc osc2 dp 1 dp 2 range dgnd ref lo ref hi in hi in lo buff c ref - c ref + common continuity int out nc f 1 , e 1 , dp 1 b 2 , c 2 , batt a 2 , g 2 , d 2 f 2 , e 2 , dp 2 b 3 , c 3 , minus a 3 , g 3 , d 3 f 3 , e 3 , dp 3 b 4 , c 4 , bc 5 a 4 , g 4 , d 4 f 4 , e 4 , dp 4 nc bp 3 bp 2 bp 1 v disp dp 4 /or nc dp 3 /ur latch/hold v+ v- int in TC7129CPL 40-pin pdip 44-pin qfp 44-pin plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 osc2 dp 1 dp 2 range dgnd ref lo ref hi in hi in lo buff c ref - c ref + common continuity int out int in v+ v- dp 3 /ur osc1 osc3 annunicator b 1 , c 1 , cont a 1 , g 1 , d 1 f 1 , e 1 , dp 1 b 2 , c 2 , lo batt a 2 , g 2 , d 2 f 2 , e 2 , dp 2 b 3 , c 3 , minus a 3 , g 3 , d 3 f 3 , e 3 , dp 3 b 4 , c 4 , bc 5 a 4 , g 4 , d 4 f 4 , e 4 , dp 4 bp 3 bp 2 bp 1 v disp dp 4 /or display output lines latch/hold ? 2002 microchip technology inc. ds21459b-page 3 tc7129 1.0 electrical characteristics absolute maximum ratings* supply voltage (v+ to v-)....................................... 15v reference voltage (ref hi or ref lo) ......... v+ to v- input voltage (in hi or in lo) (note 1) ........... v+ to v- v disp .......................................... v+ to (dgnd ? 0.3v) digital input (pins 1, 2, 19, 20, 21, 22, 27, 37, 39, 40) .......................... dgnd to v+ analog input (pins 25, 29, 30) ........................ v+ to v- package power dissipation (t a 70c) plastic dip ..................................................... 1.23w plcc ............................................................. 1.23w plastic qfp .................................................... 1.00w operating temperature range ............... 0c to +70c storage temperature range .............. -65c to +150c *stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. tc7129 electrical specifications electrical characteristics: v+ to v- = 9v, v ref =1v,t a =+25c,f clk = 120khz, unless otherwise indicated. pinnumbersreferto40-pindip. symbol parameter min typ max unit test conditions input zero input reading -0000 0000 +0000 counts v in = 0v, 200mv scale zero reading drift ? 0.5 ? v/c v in =0v,0c ? 2002 microchip technology inc. ds21459b-page 5 tc7129 2.0 pin descriptions thedescriptionsofthepinsarelistedintable2-1. table 2-1: pin function table pin no. 40-pin pdip pin no. 44-pin pqfp pin no. 44-pin plcc symbol function 1 40 2 osc1 input to first clock inverter. 2 41 3 osc3 output of second clock inverter. 3 42 4 annunciator backplane square wave output for driving annunciators. 443 5b 1 ,c 1 , cont output to display segments. 544 6a 1 ,g 1 ,d 1 output to display segments. 61 7f 1 ,e 1 ,dp 1 output to display segments. 72 8b 2 ,c 2 , lo batt output to display segments. 83 9a 2 ,g 2 ,d 2 output to display segments. 9410f 2 ,e 2 ,dp 2 output to display segments. 10 5 11 b 3 ,c 3 , minus output to display segments. 11 7 13 a 3 ,g 3 ,d 3 output to display segments. 12 8 14 f 3 ,e 3 ,dp 3 output to display segments. 13 9 15 b 4 ,c 4 ,bc 5 output to display segments. 14 10 16 a 4 ,d 4 ,g 4 output to display segments. 15 11 17 f 4 ,e 4 ,dp 4 output to display segments. 16 12 18 bp 3 backplane #3 output to display. 17 13 19 bp 2 backplane #2 output to display. 18 14 20 bp 1 backplane #1 output to display. 19 15 21 v disp negative rail for display drivers. 20 16 22 dp 4 /or input: when hi, turns on most significant decimal point. output: pulled hi when result count exceeds 19,999. 21 18 24 dp 3 /ur input: second most significant decimal point on when hi. output: pulled hi when result count is less than 1000. 22 19 25 latch /hold input: when floating, adc operates in the free run mode. when pulled hi, the last displayed reading is held. when pulled lo, the result counter contents are shown incrementing during the de-integrate phase of cycle. output: negative going edge occurs when the data latches are updated. can be used for converter status signal. 23 20 26 v- negative power supply terminal. 24 21 27 v+ positive power supply terminal and positive rail for display drivers. 25 22 28 int in input to integrator amplifier. 26 23 29 int out output of integrator amplifier. 27 24 30 continuity input: when lo, continuity flag on the display is off. when hi, continuity flag is on. output: hi when voltage between inputs is less than +200mv. lo when voltage between inputs is more than +200mv. 28 25 31 common sets common mode voltage of 3.2v below v+ for de, 10x, etc. can be used as pre-regulator for external reference. 29 26 32 c ref + positive side of external reference capacitor. 30 27 33 c ref- negative side of external reference capacitor. 31 29 35 buffer output of buffer amplifier. 32 30 36 in lo negative input voltage terminal. 33 31 37 in hi positive input voltage terminal. 34 32 38 ref hi positive reference voltage. 35 33 39 ref lo negative reference voltage tc7129 ds21459b-page 6 ? 2002 microchip technology inc. 36 34 40 dgnd internal ground reference for digital section. see section 4.3, 5v power supply. 37 35 41 range 3 a pull-down for 200mv scale. pulled hi externally for 2v scale. 38 36 42 dp 2 internal 3 a pull-down. when hi, decimal point 2 will be on. 39 37 43 dp 1 internal 3 a pull-down. when hi, decimal point 1 will be on. 40 38 44 osc2 output of first clock inverter. input of second clock inverter. ? 6,17, 28, 39 12, 23, 34, 1 nc no connection. table 2-1: pin function table (continued) pin no. 40-pin pdip pin no. 44-pin pqfp pin no. 44-pin plcc symbol function ? 2002 microchip technology inc. ds21459b-page 7 tc7129 3.0 detailed description (all pin designations refer to 40-pin pdip.) the tc7129 is designed to be the heart of a high resolution analog measurement instrument. the only additional components required are a few passive ele- ments: a voltage reference, an lcd, and a power source. most component values are not critical; substi- tutes can be chosen based on the information given below. the basic circuit for a digital multimeter application is shown in figure 3-1. see section 4.0, typical applica- tions for variations. typical values for each component are shown. the sections below give component selec- tion criteria. 3.1 oscillator (x osc ,c o1 ,c o2 ,r o ) the primary criterion for selecting the crystal oscillator is to choose a frequency that achieves maximum rejec- tion of line frequency noise. to do this, the integration phase should last an integral number of line cycles. the integration phase of the tc7129 is 10,000 clock cycles on the 200mv range and 1000 clock cycles on the 2v range. one clock cycle is equal to two oscillator cycles. for 60hz rejection, the oscillator frequency should be chosen so that the period of one line cycle equals the integration time for the 2v range: equation 3-1: this equation gives an oscillator frequency of 120khz. a similar calculation gives an optimum frequency of 100khz for 50hz rejection. the resistor and capacitor values are not critical; those shown work for most applications. in some situations, the capacitor values may have to be adjusted to com- pensate for parasitic capacitance in the circuit. the capacitors can be low cost ceramic devices. some applications can use a simple rc network instead of a crystal oscillator. the rc oscillator has more potential for jitter, especially in the least significant digit. see section 4.8, rc oscillator. 3.2 integrating resistor (r int ) the integrating resistor sets the charging current for the integrating capacitor. choose a value that provides a current between 5 a and 20 a at 2v, the maximum full scale input. the typical value chosen gives a charging current of 13.3 a: equation 3-2: toohighavalueforr int increases the sensitivity to noise pickup and increases errors due to leakage cur- rent. too low a value degrades the linearity of the integration, leading to inaccurate readings. 1/60 second = 16.7msec = 1000 clock cycles *2 osc cycles/clock cycle osc frequency i charge = 2v 150k ? 13.3 a tc7129 ds21459b-page 8 ? 2002 microchip technology inc. figure 3-1: standard circuit 3.3 integrating capacitor (c int ) the charge stored in the integrating capacitor during the integrate phase is directly proportional to the input voltage. the primary selection criterion for c int is to choose a value that gives the highest voltage swing while remaining within the high linearity portion of the integrator output range. an integrator swing of 2v is the recommended value. the capacitor value can be calculated using the following equation: equation 3-3: using the values derived above (assuming 60hz operation), the equation becomes: equation 3-4: the capacitor should have low dielectric absorption to ensure good integration linearity. polypropylene and teflon capacitors are usually suitable. a good mea- surement of the dielectric absorption is to connect the reference capacitor across the inputs by connecting: pin to pin: 20 33 (c ref +toinhi) 30 32 (c ref -toinlo) a reading between 10,000 and 9998 is acceptable; anything lower indicates unacceptably high dielectric absorption. 3.4 reference capacitor (c ref ) the reference capacitor stores the reference voltage during several phases of the measurement cycle. low leakage is the primary selection criterion for this com- ponent. the value must be high enough to offset the effect of stray capacitance at the capacitor terminals. a valueofatleast1 f is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 9v + low battery continuity v+ 5pf 120 khz 10pf 0.1 f 20 k ? 0.1 f 100k ? c int 0.1 f v+ v in ? + 330k ? crystal r o c o2 c rf d ref r ref c if r if c ref + 1 f 10k ? r bias 150k ? r int osc1 osc3 annunc v disp dp 4 /or display drive outputs dp 3 /ur latch/ hold v- v+ int in int out continuity common c ref + c ref - buff in lo in hi ref hi ref lo dgnd range dp 2 dp 1 osc2 tc7129 c o1 c int = t int xi int v swing where t int is the integration time. c int ==0.1 a 16.7msec x 13.3 a 2v ? 2002 microchip technology inc. ds21459b-page 9 tc7129 3.5 voltage reference (d ref ,r ref ,r bias ,c rf ) the reference potentiometer (r ref )providesan adjustment for adjusting the reference voltage; any value above 20k ? is adequate. the bias resistor (r bias ) limits the current through d ref to less than 150 a. the reference filter capacitor (c rf )formsan rc filter with r bias to help eliminate noise. 3.6 input filter (r if ,c if ) for added stability, an rc input noise filter is usually included in the circuit. the input filter resistor value should not exceed 100k ? . a typical rc time constant value is 16.7msec to help reject line frequency noise. the input filter capacitor should have low leakage for a high-impedance input. 3.7 battery the typical circuit uses a 9v battery as a power source. any value between 6v and 12v can be used. for oper- ation from batteries with voltages lower than 6v and for operation from power supplies, see section 4.2, powering the tc7129. 4.0 typical applications 4.1 tc7129 as a replacement part the tc7129 is a direct pin-for-pin replacement part for the icl7129. note, however, that part requires a capacitor and resistor between pins 26 and 28 for phase compensation. since the tc7129 uses internal phase compensation, these parts are not required and, in fact, must be removed from the circuit for stable operation. 4.2 powering the tc7129 while the most common power source for the tc7129 is a 9v battery, there are other possibilities. some of the more common ones are explained below. 4.3 5v power supply measurements are made with respect to power supply ground. dgnd (pin 36) is set internally to about 5v less than v + (pin 24); it is not intended as a power sup- ply input and must not be tied directly to power supply ground. it can be used as a reference for external logic, as explained in section 4.6, connecting to external logic (see figure 4-1). figure 4-1: powering the tc7129 from a 5v power supply 4.4 low voltage battery source a battery with voltage between 3.8v and 6v can be used to power the tc7129, when used with a voltage doubler circuit, as shown in figure 4-2. the voltage doubler uses the tc7660 dc-to-dc voltage converter and two external capacitors. figure 4-2: powering the tc7129 from a low voltage battery v- v+ ref hi ref lo in hi common in lo dgnd v in + ? -5v 0.1 f +5v 0.1 f 24 34 35 28 33 32 23 36 tc7129 0.1 f v- tc7129 v+ ref hi ref lo in hi common in lo dgnd 3.8v to 6v + + 10 f + 8 2 4 10 f + ? 3 tc7660 v in 5 24 34 35 28 33 32 23 36 tc7129 ds21459b-page 10 ? 2002 microchip technology inc. 4.5 +5v power supply measurements are made with respect to power supply ground. common (pin 28) is connected to ref lo (pin 35). a voltage doubler is needed, since the supply voltage is less than the 6v minimum needed by the tc7129. dgnd (pin 36) must be isolated from power supply ground (see figure 4-3). figure 4-3: powering the tc7129 from a +5v power supply 4.6 connecting to external logic external logic can be directly referenced to dgnd (pin 36), provided that the supply current of the exter- nal logic does not exceed the sink current of dgnd (figure 4-4). a safe value for dgnd sink current is 1.2ma. if the sink current is expected to exceed this value, a buffer is recommended (see figure 4-5). figure 4-4: external logic referenced directly to dgnd figure 4-5: external logic referenced to dgnd with buffer 4.7 temperature compensation for most applications, v disp (pin 19) can be connected directly to dgnd (pin 36). for applications with a wide temperature range, some lcds require that the drive levels vary with temperature to maintain good viewing angle and display contrast. figure 4-6 shows two cir- cuits that can be adjusted to give temperature com- pensation of about 10mv/c between v+ (pin 24) and v disp . the diode between dgnd and v disp should have a low turn-on voltage because v disp cannot exceed 0.3v below dgnd. v- v+ dgnd + 10 f + 8 2 4 10 f + ? 3 v in 5 24 34 35 28 33 32 23 36 tc7660 v+ gnd 0.1 f 0.1 f +5v tc7129 external logic dgnd v + 36 24 23 i logic tc7129 v- ? + external logic i logic dgnd 23 24 v+ 36 tc7129 v- ? 2002 microchip technology inc. ds21459b-page 11 tc7129 figure 4-6: temperature compensating circuits 4.8 rc oscillator for applications in which 3-1/2 digit (100 v) resolution is sufficient, an rc oscillator is adequate. a recom- mended value for the capacitor is 51pf. other values can be used as long as they are sufficiently larger than the circuit parasitic capacitance. the resistor value is calculated as: equation 4-1: for 120khz frequency and c = 51pf, the calculated value of r is 75k ? . the rc oscillator and the crystal oscillator circuits are shown in figure 4-7. figure 4-7: oscillator circuits 4.9 measuring techniques two important techniques are used in the tc7129: suc- cessive integration and digital auto-zeroing. succes- sive integration is a refinement to the traditional dual slope conversion technique. 4.10 dual slope conversion a dual slope conversion has two basic phases: inte- grate and de-integrate. during the integrate phase, the input signal is integrated for a fixed period of time; the integrated voltage level is thus proportional to the input voltage. during the de-integrate phase, the integrated voltage is ramped down at a fixed slope, and a counter counts the clock cycles until the integrator voltage crosses zero. the count is a measurement of the time to ramp the integrated voltage to zero, and is, there- fore, proportional to the input voltage being measured. this count can then be scaled and displayed as a mea- surement of the input voltage. figure 4-8 shows the phases of the dual slope conversion. figure 4-8: dual slope conversion the dual slope method has a fundamental limitation. the count can only stop on a clock cycle, so that mea- surement accuracy is limited to the clock frequency. in addition, a delay in the zero crossing comparator can add to the inaccuracy. figure 4-9 shows these errors in an actual measurement. tc7129 + ? 1n4148 5k ? 75k ? 200k ? 39k ? 19 36 24 23 v- v+ v disp dgnd tc7129 2n2222 39k ? 19 36 24 23 v- v+ v disp dgnd 20k ? 18k ? r= 0.45 freq * c tc7129 tc7129 1 40 2 270k ? 10pf v+ 120khz 5pf v+ 1 40 2 51pf 75k ? de-integrate zero crossing time integrate tc7129 ds21459b-page 12 ? 2002 microchip technology inc. figure 4-9: accuracy errors in dual slope conversion figure 4-10: integration waveform integrate de-integrate time clock pulses over shoot due to zero crossing between clock pulses integrator residue voltage over shoot caused by comparato r delay of 1 clock pulse int 1 integrate de 1 de-integrate rest x10 zero integrate and latch de 2 rest x10 de 3 zero integrate integrator residual voltage tc7129 note: shaded area g reatly expanded in time and amplitude. ? 2002 microchip technology inc. ds21459b-page 13 tc7129 4.11 successive integration the successive integration technique picks up where dual slope conversion ends. the over shoot voltage shown in figure 4-9, called the "integrator residue volt- age," is measured to obtain a correction to the initial count. figure 4-10 shows the cycles in a successive integration measurement. the waveform shown is for a negative input signal. the sequence of events during the measurement cycle is shown in table 4-1. table 4-1: measurement cycle sequence 4.12 digital auto-zeroing to eliminate the effect of amplifier offset errors, the tc7129 uses a digital auto-zeroing technique. after the input voltage is measured as described above, the measurement is repeated with the inputs shorted inter- nally. the reading with inputs shorted is a measure- ment of the internal errors and is subtracted from the previous reading to obtain a corrected measurement. digital auto-zeroing eliminates the need for an external auto-zeroing capacitor used in other adcs. 4.13 inside the tc7129 figure 4-11 shows a simplified block diagram of the tc7129. phase description int 1 input signal is integrated for fixed time (1000 clock cycles on 2v scale, 10,000 on 200 mv). de 1 integrator voltage is ramped to zero. counter counts up until zero crossing to produce reading accurate to 3-1/2 digits. residue represents an over shoot of the actual input voltage. rest rest; circuit settles. x10 residue voltage is amplified 10 times and inverted. de 2 integrator voltage is ramped to zero. counter counts down until zero crossing to correct reading to 4-1/2 digits. residue represents an under shoot of the actual input voltage. rest rest; circuit settles. x10 residue voltage is amplified 10 times and inverted. de 3 integrator voltage is ramped to zero. counter counts up until zero crossing to correct reading to 5-1/2 digits. residue is discarded. tc7129 ds21459b-page 14 ? 2002 microchip technology inc. figure 4-11: tc7129 functional block diagram figure 4-12: integrator block diagram low battery continuity segment drives backplane drives latch, decode display multiplexer up/down results counter sequence counter/decoder control logic analog section osc1 osc2 osc3 range l/h cont v+ v- dgnd common in hi in lo buff dp 1 dp 2 ur/dp 3 or/dp 4 ref hi ref lo int out int in annunciator drive v disp tc7129 common ref hi buffer integrator de zi, x10 comparator 1 200mv c ref r int c int int 1 in hi + ? ? + ? + ref lo de in lo ? + de- de+ de+ de- 100pf v ? + continuity int 1 , int 2 continuity comparator 500k ? rest to display driver 10 pf comparator 2 to digital section tc7129 int x10 ? 2002 microchip technology inc. ds21459b-page 15 tc7129 4.14 integrator section the integrator section includes the integrator, compar- ator, input buffer amplifier, and analog switches (see table 4-2), used to change the circuit configuration dur- ing the separate measurement phases described ear- lier. see integrator block diagram (figure 4-12). the buffer amplifier has a common mode input voltage range from 1.5v above v- to 1v below v+. the integra- tor amplifier can swing to within 0.3v of the rails, although for best linearity, the swing is usually limited to within 1v. both amplifiers can supply up to 80 aofout- put current, but should be limited to 20 a for good linearity. 4.15 continuity indicator a comparator with a 200mv threshold is connected between in hi (pin 33) and in lo (pin 32). whenever the voltage between inputs is less than 200mv, the continuity output (pin 27) will be pulled high, acti- vating the continuity annunciator on the display. the continuity pin can also be used as an input to drive the continuity annunciator directly from an external source (see figure 4-13). a schematic of the input/output nature of this pin is also shown in figure 4-14. figure 4-13: continuity indicator circuit figure 4-14: input/output pin schematic 4.16 common and digital ground the common and digital ground (dgnd) outputs are generated from internal zener diodes. the voltage between v+ and dgnd is the internal supply voltage for the digital section of the tc7129. common can source approximately 12 a; dgnd has essentially no source capability (see figure 4-15). table 4-2: switch legends label description label meaning. de open during all de-integrate phases. de? closed during all de-integrate phases when input voltage is negative. de+ closed during all de-integrate phases when input voltage is positive. int 1 closed during the first integrate phase (mea- surement of the input voltage). int 2 closed during the second integrate phase (measurement of the amplifier offset). int open during both integrate phases. rest closed during the rest phase. zi closed during the zero integrate phase. x10 closedduringthex10phase. x10 openduringthex10phase. com buffer 200mv in hi ? + in lo ? + v cont 500k ? to display driver (not latched) tc7129 tc7129 500k ? dp 4 /or, pin 20 dp 3 /ur, pin 21 latch/hold pin 22 continuity, pin 27 tc7129 ds21459b-page 16 ? 2002 microchip technology inc. figure 4-15: digital ground (dgnd) and common outputs 4.17 low battery the low battery annunciator turns on when supply volt- age between v- and v+ drops below 6.8v. the internal zener has a threshold of 6.3v. when the supply voltage drops below 6.8v, the transistor tied to v- turns off, pulling the "low battery" point high. 4.18 sequence and results counter a sequence counter and associated control logic pro- vide signals that operate the analog switches in the integrator section. the comparator output from the inte- grator gates the results counter. the results counter is a six-section up/down decade counter, which holds the intermediate results from each successive integration. 4.19 over range and under range outputs when the results counter holds a value greater than 19,999, the dp 4 /or output (pin 20) is driven high. when the results counter value is less than 1000, the dp 3 /ur output (pin 21) is driven high. both signals are valid on the falling edge of latch /hold (l /h) and do not change until the end of the next conversion cycle. the signals are updated at the end of each con- version, unless the l /h input (pin 22) is held high. pins 20 and 21 can also be used as inputs for external control of decimal points 3 and 4. figure 4-14 shows a schematic of the input/output nature of these pins. 4.20 latch /hold the l /h output goes low during the last 100 cycles of each conversion. this pulse latches the conversion data into the display driver section of the tc7129. this pin can also be used as an input. when driven high, the display will not be updated; the previous reading is displayed. when driven low, the display reading is not latched; the sequence counter reading will be dis- played. since the counter is counting much faster than the backplanes are being updated, the reading shown in this mode is somewhat erratic. 4.21 display driver thetc7129drivesatriplexedlcdwiththreeback- planes. the lcd can include decimal points, polarity sign, and annunciators for continuity and low battery. figure 4-16 shows the assignment of the display seg- ments to the backplanes and segment drive lines. the backplane drive frequency is obtained by dividing the oscillator frequency by 1200. this results in a back- plane drive frequency of 100hz for 60hz operation (120khz crystal) and 83.3hz for 50hz operation (100khz crystal). backplane waveforms are shown in figure 4-17. these appear on outputs bp 1 ,bp 2 ,bp 3 (pins 16, 17, and 18). they remain the same, regardless of the seg- ments being driven. other display output lines (pins 4 through 15) have waveforms that vary depending on the displayed val- ues. figure 4-18 shows a set of waveforms for the a, g, d outputs (pins 5, 8, 11, and 14) for several combina- tions of "on" segments. the annunciator drive output (pin 3) is a square wave, running at the backplane frequency (100hz or 83.3hz) with a peak-to-peak voltage equal to dgnd voltage. connecting an annunciator to pin 3 turns it on; connecting it to its backplane turns it off. + ? 12 a p tc7129 logic section 5v 3.2v n n v+ v- com dgnd 24 28 36 23 ? 2002 microchip technology inc. ds21459b-page 17 tc7129 figure 4-16: display segment assignments figure 4-17: backplane waveforms figure 4-18: typical display output waveforms bp 1 bp 2 bp 3 low battery low battery continuity f 4 , e 4 , dp 4 a 4 , g 4 , d 4 b 4 , c 4 , bc 4 f 3 , e 3 , dp 3 a 3 , g 3 , d 3 b 3 , c 3 , minus b 1 , c 1 , continuity a 1 , g 1 , d 1 f 1 , e 1 , dp 1 b 2 , c 2 , low battery a 2 , g 2 , d 2 backplane connections f 2 , e 2 , dp 2 continuity bp 1 bp 2 bp 3 v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp b segment line all off a segment on d, g off a, g on d off all on tc7129 ds21459b-page 18 ? 2002 microchip technology inc. 5.0 packaging information 5.1 package marking information package marking data not available a this time. 5.2 taping forms pin 1 component taping orientation for 44-pin plcc devices user direction of feed standard reel component orientation for tr suffix device note: drawing does not represent total number of pins. w p package carrier width (w) pitch (p) part per full reel reel size 44-pin plcc 32 mm 24 mm 500 13 in carrier tape, number of components per reel and reel size component taping orientation for 44-pin pqfp devices user direction of feed pin 1 standard reel component orientation for tr suffix device w p package carrier width (w) pitch (p) part per full reel reel size 44-pin pqfp 24 mm 16 mm 500 13 in carrier tape, number of components per reel and reel size note: drawing does not represent total number of pins. ? 2002 microchip technology inc. ds21459b-page 19 tc7129 5.3 package dimensions dimensions: inches (mm) 2.065 (52.45) 2.027 (51.49) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .555 (14.10) .530 (13.46) .610 (15.49) .590 (14.99) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .040 (1.02) .020 (0.51) 40-pin pdip (wide) pin 1 3 min. dimensions: inches (mm) .695 (17.65) .685 (17.40) .656 (16.66) .650 (16.51) .656 (16.66) .650 (16.51) .021 (0.53) .013 (0.33) .032 (0.81) .026 (0.66) .630 (16.00) .591 (15.00) .120 (3.05) .090 (2.29) .180 (4.57) .165 (4.19) .695 (17.65) .685 (17.40) .050 (1.27) typ. .020 (0.51) min. pin 1 44-pin plcc tc7129 ds21459b-page 20 ? 2002 microchip technology inc. 5.3 package dimensions (continued) dimensions: inches (mm) .557 (14.15) .537 (13.65) .398 (10.10) .390 (9.90) .031 (0.80) typ. .018 (0.45) .012 (0.30) .398 (10.10) .390 (9.90) .010 (0.25) typ. .096 ( 2.45 ) max. .557 (14.15) .537 (13.65) .083 (2.10) .075 (1.90) .041 (1.03) .026 (0.65) 7 max. .009 (0.23) .005 (0.13) 44-pin pqfp pin 1 ? 2002 microchip technology inc. ds21459b-page 21 tc7129 notes: tc7129 ds21459b-page 22 ? 2002 microchip technology inc. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. ? 2002 microchip technology inc. ds21459b-page 23 tc7129 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq ,microid, mplab,pic,picmicro,picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified. ds21459b-page 24 ? 2002 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-6766200 fax: 86-28-6766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 hong kong microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 ta iw a n microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 03/01/02 *ds21459b* w orldwide s ales and s ervice |
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